Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Mouse interface
Explanation o Mouse interface support status
PC-9801 first generation/E/F1/F2: PC-9871 first generation/K (mouse interface board) can be implemented
PC-98LT/HA, DB-P1: No mouse interface support
PC-9801F3/M2/M3: Built-in mouse interface as standard (PC-9871 compatible)
Others: Built-in mouse interface as standard
o Mouse interface type and I/O port used
------------------------------+----------------------------------------
Model | I/O port used
------------------------------+----------------------------------------
Normal (PC-9871 compatible)*1 | 7FD9-7FDFh
Normal (PC-9801VM compatible) | 7FD9-7FDFh, BFDBh, 98D7h(*2)
Normal (PC-H98) | 7FD9-7FDFh, BFDBh, 0869h, 98D7h
Hi-Res | 0061-0067h
Hi-Res (PC-H98) | 0061-0067h, 0869h, 98D7h
------------------------------+----------------------------------------
*1: Built-in PC-9871 first generation/K, PC-9801F3/M2/M3
*2: I/O 98D7h is only supported on some models
o Some 98NOTEs have a dedicated pointing device called a thumbball built-in,
but it appears to software as an external bus mouse. The thumbball and
external bus mouse are used exclusively.
o On the PC-9801P, the PEN-BIOS emulates a mouse using a pen.
It appears to software as an external bus mouse.
o For PC-98GS, PC-9821 original, Ap, As, Ae, Af, Ap2, As2, An, Ap3, As3, Ce,
Cs2, and Ce2, when the mouse conversion connector (PC-98DO/P-11) is connected
to the mouse connector, the mouse connector switches to the stick port, and an
MSX joystick can be used.
The joystick status is read from the FM sound source LSI (YM2608).
Related I/O 0188h, 018Ah
u The mouse interface and joystick port are switched at reset. The mouse
conversion connector pulls up pin 7 on the mouse connector side with a 220Ω
resistor internally. The hardware of the main unit detects this and switches
between the mouse interface and joystick port.
It is not possible to read whether the mouse conversion connector is connected
or not using software.
u The mouse interface of some models supports the middle mouse button. Pin 7
of the mouse connector is assigned to the middle button signal. However, on
models that can use a mouse conversion connector, the middle button is not
supported because pin 7 is used to check whether the mouse conversion
connector is connected.
Models that have been confirmed to support the middle button include the
PC-9871 original, PC-9801VX21/RA21/US, and PC-H98S. Models that have been
confirmed to not support the middle button, other than models that can use a
mouse conversion connector, include the PC-9821Xa.
o On the PC-9871 original/K, PC-9801F3/M2/M3, the cycle of the interrupts
generated by the mouse interface cannot be changed from software. The
interrupt cycle can be changed with a strap switch on the board. The factory
setting is 120Hz.
o On the PC-9871 original/K, the I/O port address can be changed with a DIP
switch on the board. [SW1, SW2: I/O port address]
AB15 = 0 AB7 = 1
AB14 = SW1-1 AB6 = 1
AB13 = SW1-2 AB5 = 0
AB12 = SW1-3 AB4 = 1
AB11 = SW1-4 AB3 = SW2-4
AB10 = SW2-1 AB2 = A1
AB9 = SW2-2 AB1 = A0
AB8 = SW2-3 AB0 = 1
ON=1, OFF=0
All are ON by default
* In some technical data books, AB3 may be described as undecoded, but it is actually 16-bit decoded.
Related INT 1Fh - Function 9B08h■[PC-9801P]
I/O 8C1Eh(table) bit 5,4■[PC-9801P]
I/O 8C1Eh(table) bit 5■[PC-9821Ne]
I/O 7FD9h,7FDBh,7FDDh,7FDFh
Name Input/Output of mouse interface
Target Normal (except PC-9801 first generation, E, F1, F2),
PC-9871 first generation, K (mouse interface board)
Chip Equivalent to 8255A
Function
------------+-------+-----+--------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------
7FD9h | BYTE | R/W | 8255A Port A Read/Write data
7FDBh | BYTE | R/W | 8255A Port B Read/Write data
7FDDh | BYTE | R/W | 8255A Port C Read/Write data
7FDFh | BYTE | W | 8255A Control register
------------+-------+-----+--------------------------------------------------
●7FD9h,Read/Write: 8255A Port A Read/Write data
bit 7: LEFT...Mouse left button status
1 = OFF
0 = ON
bit 6: MIDDLE...Mouse middle button status ■Undocumented
1 = OFF
0 = ON
* Not used (always 1) on some models, such as models that can connect to a mouse conversion connector (PC-98DO/P-11).
bit 5: RIGHT...Mouse right button status
1 = OFF
0 = ON
bit 4: Unused
* Value varies by model. PC-9871 (mouse interface board) is 0
bit 3-0: MD3-MD0...Counter value selected by SXY,SHL
Explanation o Sets 8255A to "Mode 0 input" and is used to obtain mouse status.
u Some models have a main BIOS that initializes 8255A, while others do not.
Models equipped with ITF ROM always initialize it. However, even if
initialization is not performed, the 8255A is set to "Mode 0 Input" upon reset.
●7FDBh,Read/Write: 8255A Port B Read/Write Data
bit 7: Unused
* In PC-98RL high-resolution mode, the status of DIP SW 1-4 can be read from
mouse interface Port B (I/O 0063h) bit 7, but cannot be read in PC-98RL normal mode.
bit 6: RAMKL...Status of DIP SW 3-6 ■[Models with built-in RAM disconnect function]
1 = Use built-in RAM from 80000 to 9FFFFh
0 = Disconnect built-in RAM from 80000 to 9FFFFh
* In PC-98RL, the status of DIP SW 3-6 can be read, but the internal RAM is not disconnected.
* The PC-9801UV21 has 640KB of built-in RAM, but the RAM cannot be disconnected with DIP SW 3-6, so this bit is unused.
bit 5: Unused
bit 4: DMA channel of the built-in HD I/F ■[PC-98RL]
1 = Use DMA channel 0
0 = Use DMA channel 1
* On page 111 of the 1993 Technical Data Book (HARDWARE edition), it is simply
stated that bit 4 of this port indicates the DMA channel of the built-in HD
I/F (set in the system setup menu), but for models other than the PC-98RL, I/O 00F6h bit 4 changes.
Related 0000:0484h bit 7,6
bit 3,2: Unused
bit 1: SPDSW...80286 clock switch status ■ [PC-9801RX2, RX21, EX, LX, DX]
1 = 10MHz
0 = 12MHz
* On page 241 of the 1993 Technical Data Book (HARDWARE edition), it is written that this bit may
indicate the i386 CPU clock, but in the survey, it only changed on machines with a 12MHz 80286 CPU.
Unused on machines other than those with a 12MHz 80286 CPU.
Related 0000:0484h bit 3-0
bit 0: Unused
Explanation o Sets the 8255A to "Mode 0 input" and is used to obtain the
status of the main unit's DIP SW, etc.
u Some models have a main unit BIOS that initializes the 8255A, while others
do not. Models equipped with ITF ROM seem to always be initialized. Even if
initialization is not performed, the 8255A is set to "Mode 0 input" when reset.
●7FDDh,Read: 8255A Port C Read Data
bits 7-4: See "Port C Write Data"
bit 3: MODSW...Normal/Hi-Res mode status ■[PC-98XL, XL^2, RL]
1 = Normal mode
* On PC-98XL, XL^2, RL, this bit reflects the status of the Hi-Res/Hi-Res mode switch.
On other models, this is undefined (PC-9801VM2, FA, etc.: 0, PC-9821: 1, etc.).
bit 2: CPUSW...Status of DIP SW 3-8 ■[Machines with 80286 or later CPUs]
1 = OFF (V30 selected)
0 = ON (80x86 selected)
* Even on machines without V30, this bit will be 1 when in V30-equivalent mode.
bit 1,0: RS-2,RS-1...DIP SW 1-6,1-5 status
1 = ON
0 = OFF
* RS-232C synchronous mode setting status. PC-9801UV2/UV21 can change RS-232C
synchronous mode with DIP SW 1-6,1-5, but it seems that the DIP SW status
cannot be read from this bit (see explanation).
Related DIP SW 1-6,1-5
Explanation o For 8255A, bits 7-4 are set to "mode 0 output" and used to
control the mouse interface. Bits 3-0 are set to "mode 0 input" and used to
obtain the status of the DIP SW on the main unit.
o Bits 3-0 are unused on PC-9871 first generation/K, PC-9801F3/M2/M3/VM2/VF/U/UV2
(no significant information can be obtained).
For the PC-9801UV21, it is not used in the Technical Data Book Supplementary
Edition, Supplementary Revised Edition, and Supplementary Revised Edition 2,
but it is described as valid in the new Technical Data Book and later.
Operation on the actual machine has not been confirmed.
For the PC-9801LV, CV, UV11, VM11, N, and PC-98DO, it is assumed to be valid
based on the description in the Technical Data Book, but the main BIOS does
not read this port.
Models equipped with ITF ROM read this port with ITF. The PC-9801VM21, UR, UF,
NV, and NL and models equipped with 80286 or later CPUs are equipped with ITF
ROM, so they support reading this port.
u Some models have a main BIOS that initializes the 8255A, while others do
not. Models equipped with ITF ROM seem to always initialize it. Even if
initialization is not performed, the 8255A is set to "mode 0 input" at reset,
so there is no problem reading bits 3 to 0. However, if you install a mouse
driver developed for the PC-9801VM etc., it may be that port C is set entirely
to output mode, making it impossible to read bits 3 to 0.
●7FDDh,Write: 8255A Port C Write Data
bit 7: HC
Control bit for the counter and latch on the mouse interface.
When this bit is changed from 0 to 1, the counter value at that time is
latched and the counter value is cleared. Details of operation are as follows.
HC
0 1
| +-------+ |
| |Rotary | +-------+ +-----+ |8255A
| |Encoder|===>|Counter|===>|Latch|====>|PORT A bit 3-0
| +-------+ +-------+ +-----+ |(MD3-MD0)
| When HC=0, the current value of the counter selected by SXY and SHL can be
| read in real time from MD3-MD0. The data passes straight through the latch.
+--+
| Reset
| +-------+ ↓ |
| |Rotary | +-------+ +-----+ |8255A
| |Encoder|===>|Counter| |Latch|====>|PORT A bit 3-0
| +-------+ +-------+ +-----+ | (MD3-MD0)
| When HC is changed from 0 to 1, the counter value at that moment is latched
| by the external circuit of the 8255A. At the same time, the counter value is
| reset to 0.
| Even if you move the mouse while HC=1, the counter value that can be read
| from MD3-MD0 does not change. If you change the SXY and SHL bits while it is
| latched, you can read the corresponding (latched) counter value.
|
| After being reset, the counter will continue to count if the mouse is moved
| while HC=1.
+--+
|
When obtaining mouse movement using a mouse driver, etc., the following
procedure is followed at regular intervals.
Change HC from 0 to 1. While keeping HC=1, change SXY and SHL to retrieve all
the contents of the counter (latch). The retrieved value indicates the amount
of mouse movement from the last time the counter contents were read to the present.
bit 6,5: SXY,SHL
11b = Upper 4 bits of data in the Y-axis direction
10b = Lower 4 bits of data in the Y-axis direction
01b = Upper 4 bits of data in the X-axis direction
00b = Lower 4 bits of data in the X-axis direction
* Selects the data to be output to MD3 to MD0
bit 4: INT#
1 = Disable interrupts
0 = Enable interrupts
* Mask control for mouse timer interrupt requests. When interrupts are
disabled, the interrupt output signal line from the mouse interface goes
into a high impedance state.
Bits 3-0: Read mode, no output possible
Explanation o For the 8255A, bits 7-4 are set to "mode 0 output" and used to
control the mouse interface. Bits 3-0 are set to "mode 0 input" and used to
obtain the status of the DIP switches on the main unit.
See "7FDDh,Read".
●7FDFh,Write: Control register
Explanation o The control register for the 8255A. For details, see the 8255A data sheet.
The initialization command issued by machines equipped with ITF ROM is 93h.
I/O BFDBh
Name Mouse interrupt timer setting
Target Normal mode for machines with built-in mouse interface (excluding PC-9801F3/M2/M3)
Chip
Function
------------+-------+-----+--------------------------------------------------
I/O address | Width | R/W | Content
------------+-------+-----+--------------------------------------------------
BFDBh | BYTE | R | Read setting value
BFDBh | BYTE | W | Mouse interrupt cycle setting
------------+-------+-----+--------------------------------------------------
●BFDBh,Read ■Undocumented
bit 7〜0: Read setting value
*Only for some models
●BFDBh,Write
bit 7〜2: 000000b=Mouse interrupt cycle setting
000010b=Unknown
bit 1,0: T1,T0...Mouse interrupt cycle
11b = 15Hz
10b = 30Hz
01b = 60Hz
00b = 120Hz (initial value at reset)
Explanation o Sets the period of interrupts generated by the mouse interface.
If bit 4 (INT#) of port C is set to 0 (interrupt enabled), interrupts will
occur periodically at the period set by this port.
o This port is not available on the original PC-9871/K, PC-9801F3/M2/M3. On
these models, the interrupt period can be changed with a strap switch on the
board. The factory setting is 120Hz.
High-resolution mode does not have the same function as this port. Interrupts
are always generated at a period of 120Hz.
u When initializing the BIOS (segment FD80h), there is a process that always
outputs 08h to I/O BFDBh (on all models from the PC-9801U onwards). The
meaning is unknown.
u On some models, when you read this port, you can read the contents that were written.
The results of the models surveyed are shown below.
PC-9801DA: Always FFh
PC-H98S: bits 7-2 = always 111111b, bits 1,0 = written value
PC-9801US: bits 3,2 = always 00b, bits 7-4,1,0 = written value
PC-9821Xa: bits 7-2 = always 000000b, bits 1,0 = written value
Related I/O 7FDDh bit 4
I/O 0869h
Name Mouse interrupt pending bit
Undocumented
Target PC-H98
Chip
Function
●Read
bit 7: Mouse interrupt pending bit
1 = Interrupt from mouse
0 = Interrupt from other device
bit 4: Mouse interrupt mode
1 = Level mode
0 = Edge mode
bit 6,5,3-0: Unknown
Explanation o PC-H98 can share interrupt signal line by setting interrupt mode
to level mode. When interrupt is shared, it is used to determine the device
that generated the interrupt in the interrupt handler.
o Bit 7 is cleared once it is read.
I/O 98D7h
Name Mouse interrupt vector setting
Undocumented
Target PC-H98, PC-9821 (except the first generation and Ce), PC-9801BA2, BS2, BX2, BA3, BX3, BX4, NS/A, NL/A
Chip
Function
[READ/WRITE]
bit 7,6: Unknown
bit 5: Unused (always 0)
bit 4-1: Mouse interrupt vector
0110b = INT6
0101b = INT5
0100b = INT41
0011b = INT3
0010b = INT2
0001b = INT1
0000b = INT0
bit 0: Mouse interrupt enable
1 = Enable
0 = Disable
Explanation o Sets the mouse interrupt vector.
I/O 0061h,0063h,0065h,0067h
Name Input/Output of Mouse Interface
Target High Resolution
Chip Equivalent to 8255A
Function
------+----+---+--------------------------------------------------
I/O Address|Width |R/W|Content
------+----+---+--------------------------------------------------
0061h |BYTE|R/W|8255A Port A Read/Write Data
0063h |BYTE|R/W|8255A Port B Read/Write Data
0065h |BYTE|R/W|8255A Port C Read/Write Data
0067h |BYTE| W |8255A Control Register
------+----+---+--------------------------------------------------
●0061h,Read/Write: 8255A Port A Read/Write Data
bit 7: LEFT...Left mouse button status
1 = OFF
0 = ON
bit 6: MIDDLE...Middle mouse button status ■Undocumented
1 = OFF
0 = ON
* Not used on PC-9821A-E02 (98 high-resolution board) (always 1).
bit 5: RIGHT...Right mouse button status
1 = OFF
0 = ON
bit 4: Unused
bit 3-0: MD3-MD0...Counter value selected by SXY, SHL
Description o Sets the 8255A to "Mode 0 input" and is used to obtain the mouse status.
●0063h,Read/Write: 8255A Port B Read/Write data
■PC-98XA
bit 7: Status of DIP SW 2-8
1 = OFF (External FDD #3,#4)
0 = ON (External FDD #1,#2)
bit 6: Status of DIP SW 2-7
Unused (1=OFF, 0=ON)
bit 5-0: Status of DIP SW 2-6-2-1
Expansion protected mode memory capacity (1=OFF, 0=ON)
000000b=0KB
000001b=256KB
000010b=512KB
:
011111b=7936KB
■Other than PC-98XA
bit 7: FDU...Status of DIP SW 1-4
1 = OFF (External FDD #3,#4)
0 = ON (External FDD #1, #2)
bit 6: Status of DIP SW 3-6 ■Undocumented
1 = OFF
0 = ON
* PC-98RL only. The status of DIP SW 3-6 can be read in the same way as in normal mode.
However, even if it is ON, the memory from 80000 to 9FFFFh is not disconnected.
bit 5: Unused
bit 4: Status of DIP SW 3-3 ■PC-98RL, PC-9821A-E10
1 = OFF (DMA channel #0 of the internal HD)
0 = ON (DMA channel #2 of the internal HD)
bit 3-1: Unused
bit 0: MOD81... 8/10MHz switch in high-resolution mode
1 = 8MHz or 16MHz
0 = 10MHz or 20MHz
Description o Set the 8255A to "Mode 0 input" and use it to get the status of the DIP SW on the main unit, etc.
●0065h,Read: 8255A Port C read data
bits 7-4: See "Port C write data"
bit 3: MODSW...Normal/Hi-Res mode status ■[PC-98XL･XL^2･RL]
0 = Hi-Res mode
* On PC-98XL･XL^2･RL, this bit reflects the status of the Hi-Res/Normal mode switch. PC-98XA is 0.
bit 2: CPUSW...DIP SW 3-8 status ■[PC-98XL･XL^2･RL]
1 = OFF (V30 selected)
0 = ON (80x86 selected)
* The status of DIP SW 3-8 can be read. Even if this switch is OFF, the V30 will not operate in Hi-Res mode.
bit 1: RS-2...RS-232C synchronous mode setting status
1 = ON
0 = OFF
* DIP SW1-10 for PC-98XA, DIP SW 1-6 for other models
bit 0: RS-1...RS-232C synchronous mode setting status
1 = ON
0 = OFF
* DIP SW1-9 for PC-98XA, DIP SW 1-5 for other models
Related DIP SW 1-6,1-5
Explanation o For the 8255A, bits 7-4 are set to "mode 0 output" and used to
control the mouse interface. Bits 3-0 are set to "mode 0 input" and used to
obtain the status of the DIP SW on the main unit, etc.
●0067h,Write: 8255A Port C Write Data
bit 7: HC
bit 6,5: SXY,SHL
11b = Y-axis direction upper 4 bits
10b = Y-axis direction lower 4 bits
01b = X-axis direction upper 4 bits
00b = X-axis direction lower 4 bits
* Select data to be output to MD3-MD0
bit 4: INT#
1 = Disable interrupt
0 = Enable interrupt
* Mask control of mouse timer interrupt request. When interrupt is disabled,
the interrupt output signal line from the mouse interface goes into high
impedance state.
bit 3-0: Output not possible because of read mode
Always set to 0000b.
Explanation o For the 8255A, bits 7-4 are set to "mode 0 output" and used to
control the mouse interface. Bits 3-0 are set to "mode 0 input" and used to
obtain the status of the DIP SW on the main unit.
See "0067h, Read" and "7FDDh, Write".
●0067h, Write: Control register
Explanation o 8255A control register. See the 8255A data sheet for details.